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ADM1041
DETAILED REGISTER DESCRIPTIONS
Table 9. Register 00h, Status1. Power-On Default XXh (Refer to the logic schematic—Figure 24.)
Bit No.
7
6
5
4
3
2
1
0
Name
ovfault
uvfault
ocpto
mfg1
mfg2
mfg3
mfg4
mfg5
R/W
R
R
R
R
R
R
R
R
Description
Overvoltage fault has occurred.
Undervoltage fault has occurred.
Overcurrent has occured and timed out (ocpf is in Status3).
MON1 flag.
MON2 flag.
MON3 flag.
MON4 flag.
MON5 flag.
Table 10. Register 01h, Status2. Power-On Default XXh (Refer to the logic schematic—Figure 24.)
Bit No.
7
6
5
4
3
2
1
0
Name
Share_OK
OrFET_OK
REVERSE_OK
V DD _OK
GND_OK
intrefok
extrefok
vddov
R/W
R
R
R
R
R
R
R
R
Description
Current share is within limits.
ORing MOSFET is on.
reverseok—No reverse voltage has occured across the ORing MOSFET.
V DD is within limits .
Connection of GND pin is good.
Internal voltage reference is within limits.
External voltage reference is within limits.
V DD is above its OV threshold.
Table 11. Register 02h, Status3. Power-On Default XXh (Refer to the logic schematic—Figure 24.)
Bit No.
7
6
5
4
3
2
1
0
Name
m_acsns_r
m_pson_r
m_penok_r
m_psonok_r
m_DC_OK_r
ocpf
PULSE_OK
fault
R/W
R
R
R
R
R
R
R
R
Description
Reflects the status on AC SENSE 1/AC SENSE 2.
Reflects the status of PSON.
Reflects the status of PEN.
Status of PS ON LINK.
Status of DC_OK.
An overcurrent has occured, direct from comparator
Pulses are present at the PULSE pin.
Fault latch.
Table 12. Register 03h, Calibration Bits. Power-On Default from EEPROM Register 8103h during Power-Up.
Bit No.
7–6
Name
rev_volt_off
R/W
R/W
Description
Reverse Voltage Detector Turn Off Threshold:
b7 b6 Function
0 0 100 mV
0 1 150 mV
1 0 200 mV
1 1 250 mV
5–4
rev_volt_on
R/W
Reverse Voltage Detector Turn On Threshold:
b5 b4 Function
0 0 20 mV
0 1 30 mV
1 0 40 mV
1 1 50 mV
3
2
gatepen
gateramp
R/W
R/W
Gatepen Option. When set, PEN is gated by acsok.
Gateramp Option. When set, soft-start is gated by acsok.
Rev. A | Page 42 of 64
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